A CMOS Buffer Without Short-Circuit Power Consumption
نویسنده
چکیده
A new CMOS buffer without short-circuit power consumption is proposed. The gatedriving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is about 15% smaller than conventional tapered CMOS buffer.
منابع مشابه
A CMOS Buffer without Short Circuit Power Consumption for Low Power Application
A new CMOS buffer without short-circuit power consumption is proposed. In this work, the gate-driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The TSPICE simulations are used to verify the operation of the buffer. It is observed that the power...
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